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IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
OE
t AW
t HZ
(7)
CE or SEM
(9)
UB , LB
(9)
t AS
(6)
t WP
(2)
t WR
(3)
R/ W
t WZ (7)
(7)
t OW
DATA OUT
DATA IN
(4)
t DW
t DH
(4)
5670 drw 10
.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5,8)
t WC
ADDRESS
t AW
CE or SEM
(9)
t AS
UB , LB (9)
R/ W
(6)
t EW (2)
t WR (3)
DATA IN
t DW
t DH
.
5670 drw 11
.
NOTES:
1. R/ W or CE or UB or LB = V IH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE = V IL and a R/ W = V IL for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W ) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/ W .
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = V IL during R/ W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t WP .
9. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . t EW must be met for either condition. CE = V IL when CE 0 = V IL
and CE 1 = V IH . CE = V IH when CE 0 = V IH and/or CE 1 = V IL .
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